Fabrication of Ultrathin Silicon-on-Insulator (SOI) Using Soitec Smart Cut® Technology

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Ultrathin Semiconductors-on-Insulators (SOI) are engineered silicon wafers designed for logic and memory chip applications, particularly those of 45nm thickness and below.  Ultrathin SOIs are two very thin silicon wafers separated by a silicon dioxide insulator—also known as a Buried Oxide layer (BOx).  The BOx is effectively a non-conducting layer that separates the two silicon conductors[1].  Ultrathin SOIs are critical to the semiconductor industry’s 22nm roadmap for increasingly thin devices such as partially depleted (PD) and fully depleted (FD) logic devices, advanced memory devices such as ZRAM, a number of advanced MOSFET devices and potentially a number of other system-on-chip applications[2]

Ultrathin SOI substrates are engineered to have top layer thicknesses ranging from a few microns down to 20nm thick, depending on customer demands.  Manufacturers can engineer the BOx layer to be as thin as 10nm.  The Smart Cut process used to make Ultrathin SOI wafers can control the uniformity and thickness down to 10 Å (Angstroms) or ±5%[3]

The fabrication process for manufacturing Ultrathin SOI chips via Soitec’s Smart Cut® technology involves a number of steps simplified as follows.  Two initial silicon wafers are used in the process—A and B.  One wafer (A) is oxidized in a high temperature high oxygen environment to create the silicon dioxide insulating layer.  An implantation process using hydrogen ions creates a weakened layer just below the surface of the oxidized coating.  Wafer A is flipped onto the non-oxidized wafer B, and is cleaved at the weakened later by the Smart Cut process. The remainder of wafer A is recycled as a new wafer A or is polished to be recycled as a new Wafer B.  Finally, the Ultrathin SOI wafer (Wafer A, B, and the insulating later) is annealed and polished using Chemical Mechanical Polishing (CMP) and touch polishing techniques.



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Smart Cut® technology allows for extremely thin precise manufacture of SOI materials for the semiconductor industry. Unibond® Ultrathin SOI wafers are approved for applications in the sub-22nm Semiconductor Industry Roadmap and are widely used in current PD 45nm logic device applications as well as advanced ultrathin memory devices.




Benefit Summary: 

Ultrathin SOIs can handle higher voltages, have reduced parasitic capacitance and operate much more efficiently at low power levels. This has a direct positive impact on resource efficiency and an indirect positive impact on environmental quality.


Risk Summary: 

Potential human and environmental health risks exist due to the use of toxic and carcinogenic chemicals used during the semiconductor manufacturing process. A number of court cases and EPA superfund designations related to semiconductor manufacturing and processing facilities support this. Environmentally, the manufacture of semiconductors is energy intensive, creating ambiguous environmental risks dependent on the energy source used during manufacturing. Storage of chemicals also poses ecological and water contamination risks as evidenced by superfund designations and the citations given to various semiconductor facilities in the last decade. Finally, the ultimate fate of the electronic devices and their chipsets pose environmental and human health risks. While these technologies will ultimately reduce resource consumption and increase energy efficiency, they do not directly address the risks associated with semiconductor manufacturing.

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